With the increasing sophistication and expertise in the fabrication of semiconductor devices, coupled with a demand for increasingly smaller die sizes, semiconductor device geometries, such as, for example, active transistor devices, are becoming smaller. The decreasing size of the active transistor devices currently requires that the interconnects contacting those active transistors also reduce in size. Presently, however, limits in photolithographic critical dimensions hamper this effort.
Currently, in an effort to reduce the width of the interconnects, those skilled in the semiconductor industry use a customized etch that causes the sidewalls of the interconnect vias to be sloped inwards. In other words, the sidewalls of the interconnect vias are not substantially vertical. Thus, where the top of the interconnect via has a width of X, the bottom of the interconnect via has a width substantially less than X. Obviously, the difference in width between the top of the interconnect via and the bottom of the interconnect via depends on the thickness of the layer the interconnect via is being formed within, as well as the sidewall angles. The result, however, is that the width of the lower portion of the interconnect via is substantially less than the width of the opening of the via. Unfortunately, this process is difficult to control.
Accordingly, what is needed in the art is a new method for forming vias in a substrate that does not experience the drawbacks of the prior art methods.